Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.4.3. Parameter Settings

Table 9.  Remote Update Intel® FPGA IP Core Parameters for Arria® II, Arria® V, Cyclone® V, Stratix® IV, and Stratix® V Devices
GUI Name Values Description
Which operation mode will you be using? REMOTE Specifies the configuration mode.
Which configuration device will you be using?
  • EPCS device
  • EPCQ device
  • MT25 device
  • MX25 device
  • MX66 device
  • S25FL device
 Choose the configuration device you are using.
Add support for writing configuration parameters — Enable this if you need to write configuration parameters.
Add support for Avalon Interface 1 — Enable this if you are using Avalon interface.
Enable reconfig POF checking — Allows you to enable .pof checking, which allows the remote update block to verify the existence of an application configuration image before the image is loaded. When you turn on this parameter, the Remote Update Intel® FPGA IP core checks the .pof and sends the reconfig signal. This option is disabled by default.

The POF checking feature detects and verifies the existence of an application configuration image before the image is loaded. Loading an invalid application configuration image may lead to unexpected behavior of the FPGA including system failure. Examples of invalid application configuration images are:

  • A partially programmed application image
  • A blank application image
  • An application image assigned with a wrong start address
When enabled, POF checking feature only checks the header section of the application image by calculating the section's CRC.
  • If the header section is invalid, the Remote Update Intel® FPGA IP does not trigger reconfiguration and asserts pof_error signal.
  • If the header section is valid, but the corruption appears in a different part of the image, the IP triggers application image reconfiguration. The reconfiguration fails due to a CRC mismatch and the nSTATUS signal asserts. The IP then loads the factory image.
1 Parameter not available in Stratix II devices.
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