AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.1. Main Link

The DisplayPort Intel® FPGA IP Main Link is a unidirectional, high-bandwidth channel used to transport video and audio data.
Figure 2. Main Link Differential Pair with FPGA Transceiver PHYThis figure shows a Main Link differential pair. The DisplayPort Intel® FPGA IP source must have AC-coupling capacitors. AC-coupling for DisplayPort Intel® FPGA IP sink is optional.

Section Content
Main Link TX
Main Link TX Electrical Specifications
Main Link RX
Main Link RX Electrical Specifications

Level Two Title