AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel Stratix® 10 E-Tile Devices

Download PDF
ID 683559
Date 11/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 915: JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9208 Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.1. Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

  • Intel® Stratix® 10 TX Signal Integrity Development Kit (Production Rev B Edition) (1ST280EY2F55E1VG) with 12 V power adapter
  • ADI AD9208 EVM
  • Micro-USB cables
  • USB type A to B cable
  • 4 SMA-to-SMA cables
  • Clock source card capable of generating ADC sampling clock and FPGA device clock frequencies as listed in the Table 6.
    Note: In this application note, the Analog Devices ADF4355 clock source card is used. Review the clocking scheme with the clock source card manufacturer of your choice.
Related Information
Level Two Title