Unique Chip ID Intel FPGA IP Core v19.1.2
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
22.1 | Resolved use of non-blocking assignments in a combinational Verilog block in the IP. | Fixed spyglass linting testing that might flag this as a warning. |
Added timing constraint to the 64-bit output port chip_id. | Fixed difficulty to close timing in the affected data output path if an ISSP is used to probe the output path. |