JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

ID 683530
Date 10/14/2022
Public
Document Table of Contents

4.3.2. Parallel I/O

Parallel I/O (PIO) modules provide general input/output (I/O) access from the Avalon® master (JTAG to Avalon® master bridge). There are two sets of 32-bit PIO registers:

  • Status registers—input from the HDL components to the Avalon® master
  • Control registers—output from the Avalon® master to the HDL components

The registers are assigned in the top level HDL file (io_status for status registers, io_control for control registers). The tables below describe the signal connectivity for the status and control registers.

Table 12.  Signal Connectivity for Status Registers
Bit Signal
0 Core PLL locked
1 TX transceiver ready (for duplex and simplex TX data path only)
2 RX transceiver ready (for duplex and simplex RX data path only)
3 Test pattern checker data error (for duplex and simplex RX data path only)
4 TX link error (for duplex and simplex TX data path only)
5 RX link error (for duplex and simplex RX data path only)
Table 13.  Signal Connectivity for Control Registers
Bit Signal
0

RX serial loopback enable (for duplex data path only)

30 Global reset
31 SYSREF