Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683505
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling the Compilation-Only Project 1.7. Compiling and Configuring the Design Example in Hardware 1.8. Testing the Hardware Design Example
1.8. Testing the Hardware Design Example x
1.8.1. Testing the Hardware Design Example using Ethernet Link Inspector 1.8.2. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.3. Design Example Interface Signals

The Low Latency 100G Ethernet Intel Stratix 10 FPGA testbench is self-contained and does not require you to drive any input signals.

Table 4.   Low Latency 100G Ethernet Intel Stratix 10 FPGA Hardware Design Example Interface Signals

Signal Direction Comments
clk50 Input Drive at 50 MHz. The intent is to drive this input from a 50 MHz oscillator on the board.
clk_ref_r Input Drive at 644.53125 or 322.265625 MHz.
cpu_resetn Input Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.
tx_serial[3:0] Output Transceiver PHY output serial data.
rx_serial[3:0] Input Transceiver PHY input serial data.
user_led[7:0] Output Status signals. Currently the design example drives all of these signals to a constant value of 0.
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