E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.11.17.3.2. Single 10G Ethernet Channel (without FEC)

Table 63.  Use Case Configuration
Data Rate Core Interface
10.3125 Gbps 64 bits

Connect o_clk_pll_div64 (161.13MHz) to the i_sl_clk_tx and i_sl_clk_rx. If you use any other source for i_sl_clk_tx or i_sl_clk_rx, make sure i_sl_clk_tx and i_sl_clk_rx have 0 PPM difference with respect to o_clk_pll_div64.

Figure 59. Ethernet 10G x 1