2.2.1. Installation Files for the UHD HDMI 2.0 Video Format Conversion Design Example
| File or Directory Name | Description |
|---|---|
| ip | Contains the IP instance files for all the Intel FPGA IP in the design. Including IP instances for :
|
| master_image | Contains pre_compiled.sof – a precompiled board programming file for the design. |
| non_acds_ip | Contains source code for additional IP in this design that the Intel Quartus Prime Design Suite does not include:
|
| sdc | Contains an SDC file that describes the additional timing constraints required by this design that are not handled by SDC files included automatically with the IP instances. |
| software | Contains source code, libraries, and build scripts for the software that runs on the embedded Nios II processor to control the high-level functionality of the design. |
| non_acds_ip.ipx | This .ipx file declares all the IP in the non_acds_ip directory to Platform Designer so it appears in the IP Library |
| pre_compile_flow.tcl | A Tcl script that the Intel Quartus project uses before compilation to automate the required build steps |
| README.txt | Brief instructions to build and run the design |
| top.qpf | The Intel Quartus Prime project file for the design |
| top.qsf | The Intel Quartus Prime project settings file for the design. This file lists all the files required to build the design, the pin assignments, and other project settings. |
| top.v | The top level Verilog HDL file for the design. |
| udx10_hdmi.qsys | The Platform Designer system containing the video processing pipeline and the Nios II processor and its peripherals. |