Low Latency 40G Ethernet Example Design User Guide

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ID 683413
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Example Design Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Example Design in Hardware
2. Example Design Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Example Design Registers
2.4. Design Variations x
2.4.1. Standard IP Core Variation 2.4.2. 40GBASE-KR4 IP Core Variation
1. Quick Start Guide
2. Example Design Description
A. Document Revision History

2.2. Hardware and Software Requirements

Altera uses the following hardware and software to test the example design:
  • Quartus Prime software
  • System Console
  • ModelSim-AE, Modelsim-SE, NCsim (Verilog only), or VCS simulator
  • Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing
Level Two Title