AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report

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ID 683405
Date 11/02/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. AN 753 Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report

1.5. Test Results

Table 7.  Results DefinitionThis table lists the possible results and their definition.

Result

Definition

PASS

The Device Under Test (DUT) was observed to exhibit conformant behavior.

PASS with comments

The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.

FAIL

The DUT was observed to exhibit non-conformant behavior.

Warning

The DUT was observed to exhibit behavior that is not recommended.

Refer to comments

From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 8.  Results

Test

L

M

F

Subclass

SCR

K

Data Rate (Gbps)

Sampling Clock (GHz)

Link Clock (MHz)

Result

1

2

2

2

1

0

16

4.9152

2.94912

122.88

PASS

2

2

2

2

1

1

16

4.9152

2.94912

122.88

PASS

3

2

2

2

1

0

32

4.9152

2.94912

122.88

PASS

4

2

2

2

1

1

32

4.9152

2.94912

122.88

PASS

5

1

2

4

1

0

16

4.9152

2.94912

122.88

PASS

6

1

2

4

1

1

16

4.9152

2.94912

122.88

PASS

7

1

2

4

1

0

32

4.9152

2.94912

122.88

PASS

8

1

2

4

1

1

32

4.9152

2.94912

122.88

PASS

The following table shows the results for test cases DL.1, DL.2, DL.3 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 9.  Results for Deterministic Latency Test

Test

L

M

F

Subclass

K

Data Rate (Gbps)

Sampling Clock (GHz)

Link Clock (MHz)

Result

DL.1

2

2

2

1

32

4.9152

2.94912

122.88

PASS

DL.2

2

2

2

1

32

4.9152

2.94912

122.88

PASS

DL.3

2

2

2

1

32

4.9152

2.94912

122.88

Pass with comments.

Link clock observed = 115 with ADC LMFC offset register set to 0.

DL.1

2

2

2

1

16

4.9152

2.94912

122.88

PASS

DL.2

2

2

2

1

16

4.9152

2.94912

122.88

PASS

DL.3

2

2

2

1

16

4.9152

2.94912

122.88

Pass with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0.

DL.1

1

2

4

1

32

4.9152

2.94912

122.88

PASS

DL.2

1

2

4

1

32

4.9152

2.94912

122.88

PASS

DL.3

1

2

4

1

32

4.9152

2.94912

122.88

Pass with comments.

Link clock observed = 195 with ADC LMFC offset register set to 0.

DL.1

1

2

4

1

16

4.9152

2.94912

122.88

PASS

DL.2

1

2

4

1

16

4.9152

2.94912

122.88

PASS

DL.3

1

2

4

1

16

4.9152

2.94912

122.88

Pass with comments.

Link clock observed = 99 with ADC LMFC offset register set to 5.

The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test case). The clock count measures the first user data output latency.

Figure 6. Deterministic Latency Measurement Ramp Test Pattern Diagram


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