Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.1 Release Notes

ID 683401
Date 8/06/2018
Public

Enhancements

Table 3.  1.0 Production to 1.1 Production Enhancements in the Intel Acceleration Stack Version
Note: No enhancements were introduced from 1.1 Beta to 1.1 Production.
Area Enhancement
Intel® Quartus® Prime Pro Edition Supports version 17.1.1
Accelerator Functional Unit (AFU) Support for 10 Gbps and 40 Gbps Ethernet MAC
  • Introduces HSSI interface to Accelerator Functional Unit (AFU)
  • Introduces 4x10G and 40G AFU examples that use HSSI interface
FPGA Interface Manager (FIM)
  • Floorplan changes to accommodate larger OpenCL* designs.
  • Timing and performance improvements to OpenCL*
  • Increase of memory-mapped I/O (MMIO) timeout
OPAE Addition of Platform Interface Manager (PIM)
DMA
  • New streaming DMA AFU.
  • Optimized DMA memory-mapped AFU driver code to improve bandwidth.
HSSI
  • Added OPAE C applications for the 10 Gbps and 40 Gbps Ethernet MAC AFU examples.
  • Added commands to pac_hssi_config.py: eqwrite, eqread and eeprom.
  • Added HSSI tuning capability to pac_hss_config.py.
  • Added driver support for HSSI.
  • Updated HSSI DEV_FEATURE_HDR (DFH) ID to 0x0A.
OpenCL*
  • Updated OpenCL* error handling to prevent spurious error messages.
  • Added environment variables to enable non-uniform memory architecture (NUMA) awareness and thread binding for DMA performance.
  • Multi-card support for aocl diagnose.
fpgainfo Tool Updated to display human readable FIM IDs that follow Acceleration Stack version numbering.
Native Loopback (NLB) AFU Added pCLK frequency information to a control and status register (CSR).
Platform Interface Manager (PIM) Updated the mechanism for finding the PIM platform class and database.