SDI Audio Intel® FPGA IP User Guide

ID 683333
Date 6/26/2023
Public
Document Table of Contents

4.3. SDI Clocked Audio Input IP Core Parameters

Table 7.  SDI Clocked Audio Input IP Core Parameters
Parameter Value Description
FIFO size 3–10

Defines the internal FIFO depth.

For example, a value of 3 means 2³ = 8.

Include Avalon® memory-mapped interface control interface On or Off

Turn on to include the Avalon® memory-mapped interface control interface.

Turning on this parameter causes the register interface signals to appear at the top level. Otherwise, the direct control interface signals appear at the top level.