Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

10.3. AXI-Stream Broadcaster IP Interfaces

Table 65.  AXI-Stream Broadcaster IP Interfaces
Name Direction Width Description
Clocks and Resets
vid_clock In 1 AXI4-S processing clock
vid_reset In 1 AXI4-S processing reset
Intel FPGA streaming video interfaces
axi4s_vid_in_tdata In 11 AXI4-S data in
axi4s_vid_in_tvalid In 1 AXI4-S data valid
axi4s_vid_in_tuser[0] In 1 AXI4-S start of video frame
axi4s_vid_in_tuser[1] In 1
  • Control or data packet (full variant)
  • Field Flag for interlaced formats (lite variant)
  • Not used (full-raster variant)
axi4s_vid_in_tuser[N-1:2] In 12 Unused
axi4s_vid_in_tlast In 1 AXI4-S end of packet
axi4s_vid_in_tready Out 1 AXI4-S data ready
axi4s_vid_out_x_tdata Out 11 AXI4-S data out
axi4s_vid_out_x_tvalid Out 1 AXI4-S data valid
axi4s_vid_out_x_tuser[0] Out 1 AXI4-S start of video frame
axi4s_vid_out_x_tuser[1] Out 1
  • Control or data packet (full variant)
  • Field flag for interlaced formats (lite variant)
  • Not used (full-raster variant)
axi4s_vid_out_x_tuser[N-1:2] Out 12 Unused
axi4s_vid_out_x_tlast Out 1 AXI4-S end of packet
axi4s_vid_out_tready In 1 AXI4-S data ready
11

The equation gives the TDATA width for these interfaces for full or lite variants:

max (floor(((bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)

The equation gives the TDATA width for these interfaces for full-raster variants:

max (floor(((bits per color sample x (number of color planes + 1) x pixels in parallel) + 7) / 8) x 8, 16)

12 This equation gives the TUSER width N for these interfaces: ceil (tdata width / 8)