Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

18.2. Frame Cleaner IP Parameters

The IP offers run-time and compile-time parameters.
Parameters Allowed range Description
Video data format
Lite mode on or off Turn on to use the lite variant of the Intel FPGA Streaming Video protocol.
Bits per color sample 8-16 Select the number of bits per color sample.
Number of color planes 1-4 Select the number of color planes per pixel.
Number of pixels in parallel 1-8 Select the number of pixels in parallel at the input and output interfaces.
Protocol settings
Discard auxiliary control packets on or off Turn on to discard all auxiliary control packets (packet types > 1). Not applicable if Lite mode is on.
Custom resolution limits on or off Turn on to apply user-set limits to the minimum and maximum field width and height reported in the outgoing image information packets. Not applicable if Lite mode is on.
Minimum field width 1-65536 Set the minimum output field width.
Maximum field width 1-65536 Set the maximum output field width.
Minimum field height 1-65536 Set the minimum output field height.
Maximum field height 1-65536 Set the maximum output field height.
Control settings
Debug features on or off Turn on for readback of frame info registers (full variant only) and debug information registers via the control agent interface.
Separate clock for control interface on or off Turn on for a separate clock for the control agent interface.
Pipeline optimization
Pipeline ready signals on or off Turn on to add extra pipeline registers to the AXI4-S tready signals.