Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/04/2022
Public

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22.3. Video Streaming FIFO IP Interfaces

Table 358.  Video Streaming FIFO IP Interfaces
Name Direction Width Description
Clocks and resets
main_clock_clk In 1 AXI4-S processing clock. Only when you turn off Dual clock.
main_reset_rst In 1 AXI4-S processing reset. Only when you turn off Dual clock
in_clock_clk In 1 AXI4-S processing clock for the input interface domain. Only when you turn on Dual clock.
in_reset_rst In 1 AXI4-S processing reset for the input interface domain. Only when you turn on Dual clock.
out_clock_clk In 1 AXI4-S processing clock for the output interface domain. Only when you turn on Dual clock.
out_reset_rst In 1 AXI4-S processing reset for the output interface domain. Only when you turn on Dual clock.

Intel FPGA streaming video interfaces

Port name Direction Width Description
axi4s_vid_in_tdata In AXI4S data in.
axi4s_vid_in_tvalid In 1 AXI4-S data valid.
axi4s_vid_in_tuser In

AXI4-S tuser

tuser[0] indicates start of video frame when asserted

tuser[1] indicates the start of a non-video packet when asserted.

axi4s_vid_in_tlast In 1 AXI4-S end of packet.
axi4s_vid_in_tready Out 1 AXI4-S data ready.
axi4s_vid_out_tdata Out 51 AXI4-S data in.
axi4s_vid_out_tvalid Out 1 AXI4-S data valid.
axi4s_vid_in_tuser Out 52

AXI4-S tuser

tuser[0] indicates start of video frame when asserted

tuser[1] indicates the start of a non-video packet when asserted.

axi4s_vid_out_tlast Out 1 AXI4-S end of packet.
axi4s_vid_out_tready In 1 AXI4-S data ready.

51

The equation gives all tdata widths in these interfaces:

max (ceil((bits per color sample x number of color planes x pixels in parallel) / 8) x 8, 16)

52

The equation gives all tuser widths in these interfaces:

N = ceil (tdata width / 8)