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1.1. Directory Structure
1.2. Generating the Design
1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench
1.4. Compiling the Compilation-Only Project
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example
2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example
2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example
2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example
2.5. Hardware Design Example Components
2.6. Design Example Interface Signals
2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
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4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
If an IP core version is not listed, the user guide for the previous IP core version applies.
| Intel® Quartus® Prime Version | IP Core Version | User Guide |
|---|---|---|
| 20.2 | 19.3.0 | H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide |
| 19.3 | 19.2.0 | H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide |
| 19.1 | 19.1 | H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide |
| 18.1 | 18.1 | H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide |
| 18.0 | 18.0 | H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide |
| 17.1 | 17.1 | Intel® Stratix® 10 H-tile Hard IP for Ethernet Design Example User Guide |