Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Public
Document Table of Contents

3.5.6. RAM Style and ROM Style—for Inferred Memory

These attributes specify the implementation for an inferred RAM or ROM block. You can specify the type of TriMatrix embedded memory block, or specify the use of standard logic cells (LEs or ALMs). The Quartus® Prime software supports the attributes only for device families with TriMatrix embedded memory blocks.

The ramstyle and romstyle attributes take a single string value. The M512, M4K, M-RAM, MLAB, M9K, M144K, M20K, and M10K values (as applicable for the target device family) indicate the type of memory block to use for the inferred RAM or ROM. If you set the attribute to a block type that does not exist in the target device family, the software generates a warning and ignores the assignment. The logic value indicates that the Quartus® Prime software implements the RAM or ROM in regular logic rather than dedicated memory blocks. You can set the attribute on a module or entity, in which case it specifies the default implementation style for all inferred memory blocks in the immediate hierarchy. You can also set the attribute on a specific signal (VHDL) or variable (Verilog HDL) declaration, in which case it specifies the preferred implementation style for that specific memory, overriding the default implementation style.

Note: If you specify a logic value, the memory appears as a RAM or ROM block in the RTL Viewer, but Integrated Synthesis converts the memory to regular logic during synthesis.

In addition to ramstyle and romstyle, the Quartus® Prime software supports the syn_ramstyle attribute name for compatibility with other synthesis tools.

These tables specify that you must implement all memory in the module or the my_memory_blocks entity with a specific type of block.

Table 31.   Applying a romstyle Attribute to a Module Declaration
HDL Code
Verilog-1995
module my_memory_blocks (...) /* synthesis romstyle = "M4K" */;
Table 32.   Applying a ramstyle Attribute to a Module Declaration
HDL Code
Verilog-2001 and SystemVerilog
 (* ramstyle = "M512" *) module my_memory_blocks (...);
Table 33.   Applying a romstyle Attribute to an Architecture
HDL Code
VHDL
architecture rtl of my_ my_memory_blocks is
attribute romstyle : string;
attribute romstyle of rtl : architecture is "M-RAM";
begin

These tables specify that you must implement the inferred my_ram or my_rom memory with regular logic instead of a TriMatrix memory block.

Table 34.  Applying a syn_ramstyle Attribute to a Variable Declaration
HDL Code
Verilog-1995
reg [0:7] my_ram[0:63] /* synthesis syn_ramstyle = "logic" */;
Table 35.  Applying a romstyle Attribute to a Variable Declaration
HDL Code
Verilog-2001 and SystemVerilog
(* romstyle = "logic" *) reg [0:7] my_rom[0:63];
Table 36.   Applying a ramstyle Attribute to a Signal Declaration
HDL Code
VHDL
type memory_t is array (0 to 63) of std_logic_vector (0 to 7);
signal my_ram : memory_t;
attribute ramstyle : string;
attribute ramstyle of my_ram : signal is "logic";

You can control the depth of an inferred memory block and optimize its usage with the max_depth attribute. You can also optimize the usage of the memory block with this attribute.

These tables specify the depth of the inferred memory mem using the max_depth synthesis attribute.

Table 37.  Applying a max_depth Attribute to a Variable Declaration
HDL Code
Verilog-1995
reg [7:0] mem [127:0] /* synthesis max_depth = 2048 */
Table 38.   Applying a max_depth Attribute to a Variable Declaration
HDL Code
 Verilog-2001 and SystemVerilog
(* max_depth = 2048*) reg [7:0] mem [127:0];
Table 39.   Applying a max_depth Attribute to a Variable Declaration
HDL Code
VHDL
type ram_block is array (0 to 31) of std_logic_vector (2 downto 0);
signal mem : ram_block;
attribute max_depth : natural;
attribute max_depth OF mem : signal is 2048;

The syntax for setting these attributes in HDL is the same as the syntax for other synthesis attributes, as shown in Synthesis Attributes.