RapidIO Intel FPGA IP Core Release Notes

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ID 683256
Date 9/28/2020
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Product Discontinuance Notification 1. RapidIO Intel FPGA IP Core Release Notes 2. RapidIO Intel FPGA IP User Guide Archives
1. RapidIO Intel FPGA IP Core Release Notes x
1.1. RapidIO Intel FPGA IP v19.2.0 1.2. RapidIO Intel FPGA IP Core v18.0 1.3. RapidIO IP Core v15.1 1.4. RapidIO IP Core v15.0 1.5. RapidIO IP Core v14.1 1.6. RapidIO IP Core v14.0 Arria 10 Edition 1.7. RapidIO IP Core v14.0 1.8. RapidIO IP Core v13.1 1.9. RapidIO IP Core v13.0
Product Discontinuance Notification
1. RapidIO Intel FPGA IP Core Release Notes
2. RapidIO Intel FPGA IP User Guide Archives

1.4. RapidIO IP Core v15.0

Table 4.  Version 15.0 May 2015
Description Impact Notes
The IP core loses lane synchronization when a lane receives three errored characters. Previously the IP core lost lane synchronization after receiving two errored characters on a lane. Lane synchronization is slightly more robust.  
Table 5.  RapidIO IP Core Signal ChangesSignals added or modified in version 15.0.
Old Signal Name New Signal Name Notes
— no_sync_indicator When this new output signal is low, it indicates at least one lane is not synchronized.
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