Intel® Arria® 10 SoC Development Kit User Guide

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ID 683227
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components 6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide A. Additional Information
1. Intel® Arria® 10 SoC Development Kit Overview x
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started x
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software 2.3. Installing the Intel® SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the Intel® FPGA Download Cable Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software x
2.2.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe* Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components x
5.1. Board Overview 5.2. Featured Device: Intel® Arria® 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. On-Board Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information x
A.1. Compliance and Conformity Statements
A.1. Compliance and Conformity Statements x
A.1.1. CE EMI Conformity Caution
1. Intel® Arria® 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide
A. Additional Information

5.9.2. 10/100/1000 Ethernet (HPS)

The development board supports an RJ-45 (HPS_P3) 10/100/1000 base-T Ethernet using an external Micrel KSZ9031RN PHY and the HPS EMAC function. The PHY-to-MAC interface employs RGMII connection using four data lines at 250 Mbps each for a connection speed of 1 Gbps.

The PHY interfaces to an RJ-45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 34. RGMII Interface between HPS (MAC) and PHY
Table 28.  Ethernet (HPS) Pin Assignments
FPGA Pin Number Shared I/O Bit Schematic Signal Name Description
H18 GPIO0_IO12 ENET_HPS_GTX_CLK EMAC0 RGMII TX Clock
H19 GPIO0_IO13 ENET_HPS_TX_EN EMAC0 RGMII enable
F18 GPIO0_IO14 ENET_HPS_RX_CLK EMAC0 RGMII RX Clock
G17 GPIO0_IO15 ENET_HPS_RX_DV EMAC0 RGMII RX DV flag
E20 GPIO0_IO16 ENET_HPS_TXD0 EMAC0 RGMII TXD0
F20 GPIO0_IO17 ENET_HPS_TXD1 EMAC0 RGMII TXD1
G20 GPIO0_IO18 ENET_HPS_RXD0 EMAC0 RGMII RXD0
G21 GPIO0_IO19 ENET_HPS_RXD1 EMAC0 RGMII RXD1
F19 GPIO0_IO20 ENET_HPS_TXD2 EMAC0 RGMII TXD2
G19 GPIO0_IO21 ENET_HPS_TXD3 EMAC0 RGMII TXD3
F22 GPIO0_IO22 ENET_HPS_RXD2 EMAC0 RGMII RXD2
G22 GPIO0_IO23 ENET_HPS_RXD3 EMAC0 RGMII RXD3
H23 GPIO1_IO8 ENETB_MDIO EMAC2 MDIO
J23 GPIO1_IO9 ENETB_MDC EMAC2 MDIO
K21 GPIO1_IO10 ENET_HPS_MDIO EMAC2 MDIO
K20 GPIO1_IO11 ENET_HPS_MDC EMAC2 MDIO

The Micrel KSZ9031RN PHY uses a multi-level POR bootstrap encoding scheme to allow a small set of I/O pins (7) to set up a very large number of default settings within the device. The related I/O pins have integrated pull-up or pull-down resistors to configure the device.

Table 29.  Ethernet PHY (HPS) Bootstrap Encoding Scheme
Board Reference (U12) Schematic Signal Name Description Strapping Option
17 ENET_HPS_LED1_LINK PHY address bit 0 Pulled high
15 ENET_HPS_LED2_LINK PHY address bit 1 Pulled high
32 ENET_HPS_RXD0 Mode 0 Pulled high
31 ENET_HPS_RXD1 Mode 1 Pulled high
28 ENET_HPS_RXD2 Mode 2 Pulled high
27 ENET_HPS_RXD3 Mode 3 Pulled high
35 ENET_HPS_RX_CLK PHY address bit 2 Pulled high
33 ENET_HPS_RX_DV Clock enable Pulled low
41 CLK125_NDO_LED_MODE Single LED mode Pulled high
Level Two Title