Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

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ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

3.7.2. Toolkit GUI Settings

The Serial Lite IV IP toolkit offers an easy-to-manage user interface.
The Serial Lite IV IP toolkit user interface has three tabs.
  • The MAC and PHY tab implements various control and status registers (CSR) for both the hardened custom PCS core and the MAC soft logic.
  • The Traffic Statistics and Bandwidth Performance tab implements various Control and Status Registers (CSR) for the Demo Management module to configure the traffic generator and checker. Additionally, it also provides a real-time bandwidth calculation measurement result based on the traffic modules instantiated in the example design.
  • The Help tab provides useful next-step troubleshooting information based on the assertion and deassertion of specific status registers or output ports if any errors happen after the link initialization is executed.

The MAC and PHY tab shows a step-by-step guide for link initialization and real-time status monitoring of a Serial Lite IV IP link.

The toolkit continuously reads and displays all of the essential status registers related to the Serial Lite IV IP link after you execute the following stages:

  1. Click Assert Full System Reset to perform a full system reset.
  2. Click Link Initialization to perform link initialization with internal/external loopback enabled..
  3. Click Read PCS Status to poll all corresponding status registers and output ports from both hardened custom PCS and MAC soft logic.
  4. Click Read FEC Statistics to generate the FEC statistics report after steps 1–3 complete successfully and the link is up and running.
Figure 21. MAC and PHY Tab
Note: The toolkit user interface changes dynamically to illustrate each execution stage.

In case of any failure, the toolkit narrows down to the type of failure based on the various status bits, which are based on the register bank or output port from the hardened custom PCS core or MAC soft logic. The corresponding next-step debugging information is displayed in the Help tab.

Figure 22. Traffic Statistics and Bandwidth Performance Tab
The Traffic Statistics and Bandwidth Performance tab enables you to configure both the traffic generator and checker in the design example to run in the user-specified traffic mode, and reads traffic statistics. You can turn on the Sink RX to Source TX parameter to run the hardware design example in slave mode. When this parameter is enabled, the traffic flows from sink to source. Additionally, the toolkit also calculates and displays the real-time effective bandwidth based on the design example.
Figure 23. Help Tab

The Help tab provides useful next-step debugging information based on the errors or status registers reported from the MAC and PCS status in the MAC and PHY tab.

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