AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Public
Document Table of Contents

1.4.1. Register Address Map

Figure 4.  Intel® Stratix® 10 Register Address Map
Notes to Figure 4:
  1. Pin[4:0]—Physical location of the pin in a lane. Refer to Appendix C: Decoding Parameter Table for more information.
  2. lane_addr[7:0]—Address of a given lane in an interface. The fitter sets this address value. Refer to Appendix C: Decoding Parameter Table for more information.
  3. Once the lane and pin addresses of the target PHY Lite for Parallel Interfaces interface is captured, the target pin can get reconfigured by Read/Write through calibration offset address, for example, cal_add = 3’b011.
  4. ID[3:0]—Interface ID parameter. This parameter distinguishes between different IP instances in an I/O column.
  5. For the physical addresses of lgc_sel and pin_off, refer to the Address Register for Pin Input Delay Feature table in the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP Core Control Registers Addresses section of the PHY Lite for Parallel Interfaces Intel® FPGA IP Core User Guide.