ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4.6.1. Single-Byte Write Operation

This figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is performing a single-byte write operation.
Figure 12. Writing a Single-ByteThe latency shown does not reflect the true processing time. The latency only shows the command.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


Single-byte write operation or when the PAGE_SIZE parameter has a value of one does not require the shift_bytes signal. Ensure that the data byte is available on the datain[7..0] signal and the memory address is available on the addr[23..0] signal before setting the write and wren signals to one.

If wren signal has a value of zero, the write operation is not carried out and the busy signal remains deasserted. If the memory region is protected (you can set this in the EPCS/EPCQ/EPCQ-L/EPCQ-A status register), then the write operation does not proceed, and the busy signal is deasserted. The IP core then asserts the illegal_write signal for two clock cycles to indicate that the command has been canceled. The write, datain[7..0], and addr[23..0] signals are registered on the rising edge of the clkin signal.

After the IP core receives the write command, it asserts the busy signal to indicate that the write operation is in progress. The busy signal stays asserted while the EPCS/EPCQ/EPCQ-L/EPCQ-A device is writing the data byte into the flash memory.

Note: If you keep both the wren and write signals asserted while the busy signal is deasserted after the IP core has finished processing the write command, the IP core re-registers the wren and write signals as a value of one and carries out another write command. Therefore, before the IP core deasserts the busy signal, you must deassert the wren and write signals.
Note: For EPCQ256 devices, the width of the addr and read_address signals is 32 bit.
Note: When writing .rpd file for FPGA configuration purposes such as the application image for remote system upgrade, you need to swap the bit order for every byte from the most significant bit (MSB) to the least significant bit (LSB). This step is required because the FPGA configuration reads data from the EPCS/EPCQ/EPCQ-L/EPCQ-A devices from LSB to MSB.
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