AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

Download PDF
ID 683191
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines x
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core 1.2. Migration Flow 1.3. AN 735 Document Revision History
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core x
1.1.1. Architecture Overview 1.1.2. Clock and Reset Scheme 1.1.3. Interface Signals
1.2. Migration Flow x
1.2.1. Instantiating Low Latency Ethernet MAC IP Core 1.2.2. Generating 156.25 MHz and 312.5 MHz Clock 1.2.3. Connecting the Low Latency Ethernet 10G MAC to Avalon-ST, Avalon-MM, and XGMII PHY Interfaces
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

1.2. Migration Flow

The Low Latency Ethernet 10G MAC IP provides adapters which allow existing users of 10GbE MAC IP core to migrate to Low Latency Ethernet 10G MAC IP with minimal modifications to the system design.

Altera recommends that you follow this migration flow.

Figure 7.  Recommended Migration Flow for Low Latency Ethernet 10G MAC IP Core



Section Content
Instantiating Low Latency Ethernet MAC IP Core
Generating 156.25 MHz and 312.5 MHz Clock
Connecting the Low Latency Ethernet 10G MAC to Avalon-ST, Avalon-MM, and XGMII PHY Interfaces

Level Two Title