AN 921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

Download PDF
ID 683163
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Device Migration Overview 3. Hardware Design Guidelines 4. Intel® Quartus® Prime Software Design Migration 5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package
3. Hardware Design Guidelines x
3.1. Power Pin Migration Guidelines 3.2. I/O Pins Migration Guidelines 3.3. VREF Pin Migration Guidelines 3.4. RZQ Pin Migration Guidelines
4. Intel® Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for 1SG040HH2F3512VG-1SG065HH3F3512VG Devices 4.2. Migration Using Migration UI for 1SX065HH3F3512LG-1SX040HH2F3512LG Devices
1. Introduction
2. Device Migration Overview
3. Hardware Design Guidelines
4. Intel® Quartus® Prime Software Design Migration
5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

3.4. RZQ Pin Migration Guidelines

This table describes the design migration guidelines for the RZQ pin for banks 3[A, B, C, D].

Table 7.  RZQ Pin Board Design Guidelines
Pin I/O Bank Board Design Guidelines
RZQ pin 3A The RZQ pin for the bank 3C at the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device must always be connected to GND, and it in not migratable to the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device or vice versa.

When using OCT for the banks 3A, 3B, and 3C, connect these pins to GND through either a 240-Ω or 100-Ω resistor, depending on the desired OCT impedance.

For more information about the OCT schemes, refer to the Intel® Stratix® 10 General Purpose I/O User Guide.

When you do not use these pins as dedicated input for the external precision resistor or as I/O pins, leave these pins unconnected as recommended in the Intel® Stratix® 10 Device Family Pin Connection Guidelines.

3B
3C
3D
Figure 7. RZQ Pin for Banks 3[A, B, C, D]
Related Information
Level Two Title