Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

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ID 683149
Date 8/18/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview x
1.1. Intel® Stratix® 10 MX Devices 1.2. Innovations in Intel® Stratix® 10 MX Devices 1.3. Intel® Stratix® 10 MX Features Summary 1.4. Intel® Stratix® 10 MX Block Diagram 1.5. Intel® Stratix® 10 MX Family Plan 1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.7. Intel® Hyperflex™ Core Architecture 1.8. Heterogeneous 3D SiP Transceiver Tiles 1.9. Intel® Stratix® 10 MX Transceivers 1.10. PCI Express Gen1/Gen2/Gen3 Hard IP 1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP 1.12. 10G Ethernet Hard IP 1.13. Interlaken PCS Hard IP 1.14. External Memory and General Purpose I/O 1.15. Adaptive Logic Module (ALM) 1.16. Core Clocking 1.17. Fractional Synthesis PLLs and I/O PLLs 1.18. Internal Embedded Memory 1.19. Variable Precision DSP Block 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1.5. Intel® Stratix® 10 MX Family Plan x
1.5.1. Available Options
1.9. Intel® Stratix® 10 MX Transceivers x
1.9.1. PMA Features 1.9.2. PCS Features
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

Document Version Changes
2022.08.18 Made the following change:
  • Removed the details of Register state readback and writeback feature from Key Features of Intel Stratix 10 MX Devices Compared to Stratix V Devices table.
  • Removed readback and writeback feature from advatnages in Device Configuration and Secure Device Manager (SDM) section.
2022.08.08 Updated the sample ordering code and available options:
  • Updated the H-Tile maximum data rate for –2 transceiver speed grade from 26.0 Gbps to 26.6 Gbps
  • Updated the E-Tile maximum data rate (NRZ) for –1 transceiver speed grade from 30.0 Gbps to 28.9 Gbps
2020.09.28 Made the following change:
  • Added black key provisioning (-BK) devices. See the "Sample Ordering Code" figure in Available Options.
2020.03.24 Made the following change:
  • Added advanced security (-AS) devices.
2019.08.19 Made the following change:
  • Added composition details for the leaded and lead-free contact device options.
2019.03.13 Made the following changes:
  • Updated maximum transceiver data rates from 30 Gbps NRZ to 28.9 Gbps NRZ.
  • Updated data in the " Intel® Stratix® 10 MX Family Plan—Interconnects, PLLs, Hard IP, and HBM2 (part 2)" table.
2019.02.15 Made the following changes:
  • Changed the number of eSRAM memory block to 47.25 Mbit and the number of embedded memory to 94.5 Mbits.
  • Changed the number of maximum transceiver data rate to 57.8 Gbps.
  • Removed the descriptions of the Hard Processor System (HPS) block.
  • Removed the MX 1100 density device from family and package plans.
2018.08.09 Made the following changes:
  • Changed the direction arrow from the coefficient registers block in the "DSP Block: High Precision Fixed Point Mode" figure.
  • Changed the descriptions for the core process technology and power management features in the " Intel® Stratix® 10 MX Device Features" table.
  • Changed the power option description in the "Sample Ordering Code and Available Options for Intel® Stratix® 10 MX Devices" figure.
  • Changed the description of the SmartVID in the "Power Management" section.
2018.04.18 Made the following change:
  • Changed the description of the logic densities in the "Sample Ordering Code and Available Options for Intel® Stratix® 10 MX Devices" figure.
2018.03.05 Made the following change:
  • Changed the number of eSRAM banks per channel to 42 in the "Internal Embedded Memory" section.
2018.02.27 Made the following change:
  • Corrected the package body size for the F2597 package in the " Intel® Stratix® 10 MX Package Plan" table.
2017.10.30 Made the following changes:
  • Changed the description for the Embedded Memory (M20K) feature in the "Key Features of Intel® Stratix® 10 MX Devices Compared to Stratix V Devices" table.
  • Changed the number of 18x19 multipliers in the "Key Features of Intel® Stratix® 10 MX Devices Compared to Stratix V Devices" table.
  • Changed the total number of General purpose I/Os available in the " Intel® Stratix® 10 MX Device Features" table.
  • Changed the resource availabilities for the MX 1650 and MX2100 devices in the " Intel® Stratix® 10 MX Family Plan—FPGA Core (part 1)" table.
  • Changed the maximum GPIOs and Maximum XCVR availabilities for the MX 1650 and MX 2100 devices in the " Intel® Stratix® 10 MX Family Plan—Interconnects, PLLs, Hard IP, and HBM2 (part 2)" table.
  • Changed the resource counts for the F2597 package in the " Intel® Stratix® 10 MX Package Plan" table.
2017.07.17 Initial release.
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