Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Clock Multiplexer Constraints Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Clock Multiplexing

With clock multiplexing, you can select from two or more clocks with the create_clock and set_clock_groups constraints.
Figure 7. Constraints for a Typical 2:1 Clock Multiplexer

Clock Multiplexer Constraints

#Create the first input clock clkA to the mux
create_clock -period 10.000 -name clkA [get_ports {clkA}]
#Create the second input clock clkB to the mux
create_clock -period 20.000 -name clkB [get_ports {clkB}]
#Cut paths between clkA and clkB
set_clock_groups 	-exclusive 	-group {clkA} 	-group {clkB}
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