Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 10/02/2023
Public
Document Table of Contents

5.2. Supported Operational Modes

Table 39.  Operational Modes Supported by Native Fixed Point DSP Intel Agilex® FPGA IP Core
Operational Modes Description
9 × 9 Sum of 4 Mode

This mode operates as sum of four 9 (signed) × 9 (signed) or 8 (unsigned) × 8 (unsigned) multipliers with 20 to 64 bits output when chainout adder or accumulator is enabled.

This mode applies the following equations:
  • resulta = (ax * ay)+(bx * by)+(cx * cy)+(dx * dy)
18 × 18 Full Mode This mode operates as two independent 18 (signed) x 19 (signed) or 18 (unsigned) x 18 (unsigned) multipliers with 37-bit output.
This mode applies the following equation:
  • resulta = ax * ay
  • resultb = bx * by
18 × 18 Sum of Two Mode This mode operates as sum of two 18 × 19 multiplication.
This mode applies the equations of:
  • resulta = [(bx * by) + (ax * ay)] when sub signal is driven low.
  • resulta = [(bx * by) - (ax * ay)] when sub signal is driven high.

The resulta output bus can support up to 64 bits when you enable accumulator or chainout adder.

18 × 18 Plus 36 Mode

This mode operates as one 18 × 19 multiplication summed to a 36-bit input.

This mode applies the equation of resulta = (ax * ay) + (bx * by).

When the input bus is less than 36-bit in this mode, you are required to provide the necessary signed extension to fill up the 36-bit input.

When you enable the accumulator, the resulta output bus can support up to 64 bits.

18 × 18 Systolic Mode

This mode operates as 18-bit systolic FIR.

Enable the input systolic register and the output register when using this operational mode.

When you enable the chainout adder, the chainout and chainin width can support up to 44 bits.

When you enable the accumulator, the resulta output bus can support up to 64 bits.

27 × 27 Mode

This mode operates as one independent 27(signed/unsigned) × 27(signed/unsigned) multiplier.

This mode applies the equation of resulta = ax * ay.

The resulta output bus can support up to 64 bits when you enable accumulator or chainout adder.