Serial Digital Interface (SDI) II Intel® FPGA IP Release Notes

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Date 4/09/2024
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1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes
1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes x
1.1. SDI II Intel® FPGA IP v19.5.0 1.2. SDI II Intel® FPGA IP v19.4.0 1.3. SDI II Intel® FPGA IP v19.3.2 1.4. SDI II Intel® FPGA IP v19.3.0 1.5. SDI II Intel® FPGA IP v19.2.1 1.6. SDI II Intel® FPGA IP v19.2 1.7. SDI II Intel® FPGA IP v19.1 1.8. SDI II Intel® FPGA IP v18.1 Update 2 1.9. SDI II Intel® FPGA IP v18.1 Update 1 1.10. SDI II Intel® FPGA IP v18.1 1.11. SDI II Intel® FPGA IP v18.0 1.12. Intel FPGA SDI II IP Core v17.1 1.13. SDI II IP Core v17.0 1.14. SDI II IP Core v16.1 1.15. SDI II IP Core v16.0 1.16. SDI II IP Core v15.1 1.17. SDI II IP Core v15.0 1.18. SDI II IP Core v14.1 1.19. Serial Digital Interface (SDI) II User Guide Archives
1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes

1.11. SDI II Intel® FPGA IP v18.0

Table 10.  v18.0 May 2018
Description Impact
Renamed Intel FPGA SDI II IP to SDI II Intel® FPGA IP as part of standardizing and rebranding exercise. –
Added support for Xcelium* Parallel simulator. These changes are optional. If you do not upgrade your IP core, it does not have these new features.

Added a new parameter, Rx core clock (rx_coreclk) frequency. This parameter is available only when you select Multi rate (up to 12G) and Receiver or Bidirectional direction in the Quartus® Prime Pro Edition software.

Updated the rx_coreclk_is_ntsc_paln signal to include 297.0 MHz and 296.70 MHz options.
Added Parallel loopback without external VCXO option for Stratix® 10 design example.
Added the following files:
  • pid_controller.v
  • rcfg_pll_frac.v
  • modelsim_files.tcl
  • ncsim_files.tcl
  • riviera_files.tcl
  • vcs_files.tcl
  • vcsmx_files.tcl
  • xcelium_files.tcl
  • tb_ln_check.v
  • cds.lib
  • hdl.var
  • xcelium_setup.sh
  • xcelium_sim.sh
Added final support for Cyclone® 10 GX devices. The Cyclone® 10 GX devices are only available in the Quartus® Prime Pro Edition software.
Added new design examples for Cyclone® 10 GX devices in version 17.1.1 release. Refer to the SDI II Intel Cyclone 10 GX FPGA IP Design Example User Guide for more information.
Table 11.  Design Files Required for IP Upgrade

The implementation of the IP on hardware requires additional components specific to the device targeted.

These additional components, such as Native PHY, TX PLL, reconfiguration controller, are not included as part of the Quartus® Prime IP Upgrade flow. Upgrading an IP core would require the inclusion of these files generated as part of the IP design example.

Design Example Required Files
Arria® 10
  • sdi_ii_a10_demo.v
  • sdi_ii_a10_demo.sdc
  • edge_detector.sv
  • clock_heartbeat.sv
  • a10_reconfig_arbiter.sv
  • Files inside the <vid_pattgen> folder
  • Files inside <loopback> folder
  • Files inside <du>, or <rx> and <tx> folders
Cyclone® 10 GX
  • sdi_ii_a10_demo.v
  • sdi_ii_a10_demo.sdc
  • edge_detector.sv
  • clock_heartbeat.sv
  • a10_reconfig_arbiter.sv
  • Files inside the <vid_pattgen> folder
  • Files inside <loopback> folder
  • Files inside <du>, or <rx> and <tx> folders
Stratix® 10
  • sdi_ii_a10_demo.v
  • sdi_ii_a10_demo.sdc
  • edge_detector.sv
  • clock_heartbeat.sv
  • a10_reconfig_arbiter.sv
  • Files inside the <vid_pattgen> folder
  • Files inside <loopback> folder
  • Files inside <du>, or <rx> and <tx> folders
  • Files inside <mr_phy_adapter> folder
Related Information
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