GTS Interlaken Intel® FPGA IP Design Example User Guide

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ID 819203
Date 3/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS Interlaken FPGA IP Design Example User Guide Archives 4. Document Revision History for GTS Interlaken FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. GTS Interlaken FPGA IP Design Example User Guide Archives
4. Document Revision History for GTS Interlaken FPGA IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 3.0.0

The GTS Interlaken Intel® FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design.

The testbench and design example supports NRZ mode for GTS devices. The GTS Interlaken Intel® FPGA IP core generates design examples for the following supported combinations of number of lanes and data rates.

Table 1.  IP Supported Combinations of Number of Lanes and Data RatesThe following combinations are supported in the Quartus® Prime Pro Edition software version 24.1
Number of Lanes Lane Rate (Gbps)
6.25 12.5
4 Yes Yes
6 - -
8 - Yes
Figure 1. Development Steps for the Design Example
The GTS Interlaken Intel® FPGA IP core design example supports the following features:
  • Internal TX to RX serial loopback mode
  • Automatically generates fixed size packets
  • Basic packet checking capabilities
  • Ability to use System Console to reset the design for re-testing purpose
Figure 2. High-level Block Diagram

Section Content
Software Requirements
Generating the Design
Directory Structure
Simulating the Design Example Testbench
Compiling and Configuring the Hardware Design Example

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