AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel Agilex® 7 FPGA Development Board

Download PDF
ID 750856
Date 2/14/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board

Reference Design Walkthrough

Level Two Title