DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide

ID 683603
Date 4/29/2024
Public
Document Table of Contents

1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 21.0.1
The DisplayPort Intel® FPGA IP design examples for Cyclone® 10 GX devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.

The DisplayPort Intel® FPGA IP offers the following design examples:

  • DisplayPort SST TX-only
  • DisplayPort SST RX-only
  • DisplayPort SST parallel loopback with a Pixel Clock Recovery (PCR) module
  • DisplayPort SST parallel loopback without a PCR module
  • DisplayPort MST parallel loopback with a PCR module
  • DisplayPort MST parallel loopback without a PCR module
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Steps