1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Release Notes

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ID 683019
Date 4/01/2024
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1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP (intel_mge_phy) Release Notes 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP (alt_mge_phy) Release Notes
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP (intel_mge_phy) Release Notes x
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP (intel_mge_phy) v2.1.0
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP (alt_mge_phy) Release Notes x
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v22.0.0 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v21.0.2 1G/2.5G/5G/10G Multirate Ethernet PHY v21.0.1 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v20.1.0 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v20.0.0 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v19.3.0 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v19.1 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v18.0 1G/2.5G/5G/10G Multirate Ethernet PHY IP Core v17.1 1G/2.5G/5G/10G Multirate Ethernet PHY v16.0 1G/2.5G/10G Multirate Ethernet PHY v15.1
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP (intel_mge_phy) Release Notes
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP (alt_mge_phy) Release Notes

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP v19.1

Table 5.  v19.1 April 2019
Description Impact
Renamed the Enable Altera Debug Master Endpoint parameter to Enable Native PHY Debug Master Endpoint as per Intel® rebranding in the Intel® Quartus® Prime Pro Edition software. The Intel® Quartus® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint. —
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