Intel® Cyclone® 10 10CL010 FPGA
Specifications
Compare Intel® Products
Essentials
-
Product Collection
Intel® Cyclone® 10 LP FPGA
-
Marketing Status
Launched
-
Launch Date
2017
-
Lithography
60 nm
Sign in with your CNDA account to view additional SKU details.
Resources
I/O Specifications
-
Maximum User I/O Count†
176
-
I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3 V LVCMOS, PCI, PCI-X, SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, Mini-LVDS, RSDS, PPDS, LVPECL, BLVDS
-
Maximum LVDS Pairs
65
Package Specifications
-
Package Options
M164, U256, E144
Supplemental Information
-
Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
Sign in with your CNDA account to view additional SKU details.
Ordering and spec information
Trade compliance information
- ECCN EAR99
- CCATS NA
- US HTS 8542390001
PCN Information
SR6SC
- 968086 PCN
SR4CL
- 965229 PCN
SR4CK
- 965228 PCN
SR4CJ
- 965227 PCN
SR6GK
- 967736 PCN
SR7CV
- 968795 PCN
SR6GJ
- 967735 PCN
SR5YK
- 967111 PCN
SR6SD
- 968087 PCN
Drivers and Software
Description
Type
More
OS
Version
Date
All
View Details
Download
No results found for
Y
/apps/intel/arksuite/template/arkProductPageTemplate
Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.