Ethernet
Interface protocols enable chip-to-chip, board-to-board, or box-to-box connectivity in system designs. Protocol intellectual property (IP) solutions from Intel and our partners satisfy the needs of a broad spectrum of applications and leverage the integrated transceivers in our FPGA and ASIC devices. Interface protocol solutions are delivered as licensable IP cores and reference designs as well as no-cost megafunctions and design examples.
Visit Transceiver Protocols section to learn more about the integrated transceivers and their supporting interface protocol solutions.
Design Examples |
Device Targeted |
Development Kits Supported |
Qsys Compliant |
Quartus II Version |
---|---|---|---|---|
Constraint RGMII Interface of Triple Speed Ethernet with the External PHY Delay Feature |
Cyclone® II, Cyclone III, Cyclone III LS, Cyclone IV GX, Stratix® II, Stratix II GX, Stratix III, Stratix IV, Arria® GX, Arria® II GX |
Stratix IV GX FPGA Development Kit, Arria II GX FPGA Development Kit |
- |
10.1 |
Stratix IV GX |
Stratix IV GX FPGA Development Kit |
✓ |
12.1 |
|
Cyclone III , Stratix IV GX |
Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit, CV GT FPGA Development Kit |
✓ |
12.0 |
|
Cyclone III |
Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
- |
13.1 |
|
Cyclone III |
Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
- |
10.1 |
|
TSE: Implement Reset Sequence in TSE Using ALTGX as Transceiver |
Stratix IV GX |
- |
- |
9.1 SP1 |
TSE: Implement Reset Sequence in TSE Using ALTLVDS as Transceiver |
Stratix IV GX |
- |
- |
9.1 SP1 |
Stratix IV GX , Arria II GX |
- |
- |
9.1 SP1 |