Article ID: 000087095 Content Type: Troubleshooting Last Reviewed: 02/08/2013

CvP Update Stress Tests Might Fail in Arria V GZ Designs that Include the Transceiver Reconfiguration Controller

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    CvP update stress tests might fail when a Stratix V GX Hard IP for PCI Express IP Core design also includes the Transceiver Reconfiguration Controller IP Core. This hardware issue does not affect CvP initialization.

    Resolution

    For some systems, removing the Transceiver Reconfiguration Controller IP Core from the system design and tying the Avalon Memory-Mapped (Avalon-MM) interface_sel signal for each channel or PLL to 1’b1 resolves this issue. The interface_sel signal is reconfig_to_xcvr[44] of each channel or PLL. However, this workaround prevents you from assigning different protocols to the 6 channels in a transceiver bank. A comprehensive solution is under investigation.

    Related Products

    This article applies to 1 products

    Arria® V GZ FPGA