Article ID: 000086681 Content Type: Product Information & Documentation Last Reviewed: 07/28/2017

How can the Arria 10 EMIF Traffic Generator be set for infinite loop test?

Environment

  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When generating an Arria®10 EMIF example design, a traffic generator is implemented by default, but the traffic generator settings can't be configured through Qsys.

     

    Resolution

    After generating the HDL for the Arria 10 EMIF example design, change the Qsys IP top files with the generic parameter as below:

      .TEST_DURATION                      ("INFINITE"),

    The traffic generator will perform read/write tests infinitely. 

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs