The true differential I/O standard voltage requirement for Stratix® II, Stratix II GX, Arria™ GX and HardCopy® II devices depends on the location of the true differential buffer.
Most of the LVDS buffers are located on the side I/O banks. This is where the dedicated SERDES circuitry is located and can be accessed by the side bank LVDS I/O pins. This is the common location for most LVDS operations. These banks require a 2.5V VCCIO for both LVDS input and output operations.
Banks 3, 4, 7, and 8 located on the top and bottom of the device support input only operations for LVDS/LVPECL on the dedicated clock input buffers. These buffers use VCCINT for LVDS/LVPECL operations and have no dependency on the bank VCCIO voltage. These banks do not support LVDS/LVPECL output operations.
Banks 9, 10, 11, and 12 require a 3.3V VCCIO for both LVDS/LVPECL input and output operations. LVDS/LVPECL output operations are supported on the PLL[5,6,11,12]_OUT[0,1] pins. LVDS/LVPECL input or output operations are supported on the PLL[5,6,11,12]_FB/OUT2 pins. These are the only pins that can be configured to be LVDS/LVPECL inputs or configured to be LVDS/LVPECL outputs.
Stratix II, Stratix II GX, and HardCopy II devices do not support bidirectional LVDS/LVPECL pins.