Description
In the Quartus® II software version 15.0, the JESD204B IP core may fail to meet setup timing at data rates above 7.50Gbps (IP core link clock rates above 187.5MHz) in Arria® V GT and ST devices.
Resolution
To close timing, use the following settings:
- Optimization Mode: Performance (High Effort - increase runtime)
-
Advanced Settings (Fitter)
-
Fitter Effort: Standard Fit
-
Perform Clocking Topology Analysis During Routing: On
-
Perform Physical Synthesis for Combinational Logic for Performance: On
-
Perform Register Duplication for Performance: On
-
Perform Register Retiming for Performance: On
-
Placement Effort Multiplier: 4.0
-
Router Timing Optimization Level: Maximum
If timing failures still exist, take the following actions:
-
Over-constrain the link clock (IP core clock domain) by 10-15% in user Synopsys Design Constraint (.sdc) file and close timing at the targeted frequency in TimeQuest. For example, if the 187.5MHz link clock is generated by core PLL, constrain the 187.5MHz core PLL reference clock (clock name is device_clk) with 260MHz (12%) using the create_clock command:
set current_exe == $::TimeQuestInfo(nameofexecutable)
if { == "quartus_fit"} {
create_clock -name device_clk -period 3.85 [get_ports device_clk]
} else {
create_clock -name device_clk -period 5.33 [get_ports device_clk]
}
-
Use Design Space Explorer II to perform fitter seed sweeping to determine the optimal Fitter Initial Placement Seed number.