Article ID: 000084951 Content Type: Troubleshooting Last Reviewed: 09/02/2012

What are the TimeQuest equivalent SDC constraints for QDR II SRAM legacy controller read capture registers in a Stratix II device?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The equivalent TimeQuest SDC constraints for QDRII SRAM legacy controller read capture in startix® II device are:

set_max_delay -0.2 -from * -to resync*
set_min_delay -1.6 -from * -to resync*

These constraints in Quartus® II software static Timing Analysis (TAN) are:

set_instance_assignment -name SETUP_RELATIONSHIP "– 0.2 ns" -from * – to resync*
set_instance_assignment -name HOLD_RELATIONSHIP "– 1.6 ns" -from * – to resync* 

Related Products

This article applies to 1 products

Stratix® II FPGAs