Article ID: 000084678 Content Type: Troubleshooting Last Reviewed: 05/20/2013

What is the supported frequency for scanclk and mgmt_clk for the Altera_PLL and Altera_PLL_RECONFIG megafunctions?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description The supported frequency for scanclk and mgmt_clk used by the Altera_PLL and Altera_PLL_RECONFIG megafunctions is defined by fDYCONFIGCLK in the respective device Datasheet. 

fDYCONFIGCLK is the Dynamic Configuration Clock.

Related articles

Related Products

This article applies to 15 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.