To work around the problem, find and edit the Qsys generated <module name>_hw.tcl file for the component in the error message.
Make the signal names unique between all avalon_streaming sinks, and between all avalon_streaming sources. For example you can add a "1" to all the names on one component.
Also comment out the "exp" interface.
For example:
Qsys generated version:
...
# Interface AStInput
add_interface AStInput avalon_streaming sink
set_interface_property AStInput errorDescriptor ""
set_interface_property AStInput maxChannel 255
set_interface_property AStInput readyLatency 0
set_interface_property AStInput ASSOCIATED_CLOCK clock
set_interface_property AStInput ENABLED true
set_interface_property AStInput dataBitsPerSymbol 17
add_interface_port AStInput input_ready ready Input 1
set_port_property input_ready VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput sink_valid valid Input 1
set_port_property sink_valid VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput sink_channel channel Input 8
add_interface_port AStInput sink_data data Input 17
add_interface_port AStInput sink_sop startofpacket Input 1
set_port_property sink_sop VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput sink_eop endofpacket Input 1
set_port_property sink_eop VHDL_TYPE STD_LOGIC_VECTOR
# Interface AStInput1
add_interface AStInput1 avalon_streaming sink
set_interface_property AStInput1 errorDescriptor ""
set_interface_property AStInput1 maxChannel 255
set_interface_property AStInput1 readyLatency 0
set_interface_property AStInput1 ASSOCIATED_CLOCK clock
set_interface_property AStInput1 ENABLED true
set_interface_property AStInput1 dataBitsPerSymbol 17
add_interface_port AStInput1 input_ready ready Input 1
set_port_property input_ready VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput1 sink_valid valid Input 1
set_port_property sink_valid VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput1 sink_channel channel Input 8
add_interface_port AStInput1 sink_data data Input 17
add_interface_port AStInput1 sink_sop startofpacket Input 1
set_port_property sink_sop VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput1 sink_eop endofpacket Input 1
set_port_property sink_eop VHDL_TYPE STD_LOGIC_VECTOR...
# Interface exp
add_interface exp conduit end
set_interface_property exp ENABLED true
Modified version:
# Interface AStInput
add_interface AStInput avalon_streaming sink
set_interface_property AStInput errorDescriptor ""
set_interface_property AStInput maxChannel 255
set_interface_property AStInput readyLatency 0
set_interface_property AStInput ASSOCIATED_CLOCK clock
set_interface_property AStInput ENABLED true
set_interface_property AStInput dataBitsPerSymbol 17
add_interface_port AStInput input_ready ready Input 1
set_port_property input_ready VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput sink_valid valid Input 1
set_port_property sink_valid VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput sink_channel channel Input 8
add_interface_port AStInput sink_data data Input 17
add_interface_port AStInput sink_sop startofpacket Input 1
set_port_property sink_sop VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput sink_eop endofpacket Input 1
set_port_property sink_eop VHDL_TYPE STD_LOGIC_VECTOR
# Interface AStInput1
add_interface AStInput1 avalon_streaming sink
set_interface_property AStInput1 errorDescriptor ""
set_interface_property AStInput1 maxChannel 255
set_interface_property AStInput1 readyLatency 0
set_interface_property AStInput1 ASSOCIATED_CLOCK clock
set_interface_property AStInput1 ENABLED true
set_interface_property AStInput1 dataBitsPerSymbol 17
add_interface_port AStInput1 input1_ready ready Input 1
set_port_property input1_ready VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput1 sink1_valid valid Input 1
set_port_property sink1_valid VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput1 sink1_channel channel Input 8
add_interface_port AStInput1 sink1_data data Input 17
add_interface_port AStInput1 sink1_sop startofpacket Input 1
set_port_property sink1_sop VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port AStInput1 sink1_eop endofpacket Input 1
set_port_property sink1_eop VHDL_TYPE STD_LOGIC_VECTOR...
# Interface exp
# add_interface exp conduit end
# set_interface_property exp ENABLED true
This is scheduled to be fixed in a future release of the Quartus II/DSP Builder software.