Article ID: 000084096 Content Type: Troubleshooting Last Reviewed: 03/16/2023

Why are there timing violations within my PLL Reconfig Intel® FPGA IP?

Environment

  • Avalon ALTPLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The maximum frequency for the mgmt_clk and scanclk reconfiguration clock inputs for PLL reconfiguration are specified in the respective device datasheets for Stratix® V, Arria® V, and Cyclone® V devices with the symbol tDYCONFIGCLK.

     

    Resolution

    The PLL Reconfig Intel® FPGA IP might require a lower clock frequency to achieve timing closure.  You should use the Timing Analyzer to ensure that your choice of clock frequency for mgmt_clk and/or scanclk will meet the timing requirements of your chosen device.

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