Article ID: 000081478 Content Type: Troubleshooting Last Reviewed: 04/12/2023

Why do I receive a fitting error when trying to place the HPS SPI controller clock?

Environment

  • Quartus® II Software
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might receive a fitting error when compiling your Cyclone® V SoC based design if the sclk_out pin associated with the HPS SPI Controller sclk_out pin is assigned to a pin that is not accessible by one of the Regional Clock (RCLK) networks that the sclk_out port on the HPS has access to.

     Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 auto-promoted clock driver(s))

    Resolution

    The HPS SPI controller sclk_out port can access clock networks RCLK[76:81] and RCLK[0:9].

    If the sclk_out port needs to access resources outside of these regions, an LCELL primitive must be used to allow other interconnect to be used.

    Related Products

    This article applies to 3 products

    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA