Critical Issue
Description
Yes, the PCI® Master/Target core can be used as Master-only without Target capability in SOPC as Host-Bridge mode.
The command register of I/O enable (io_ena) and Memory enable (men_en) bits will be set to zero by default after reset, so the default value of the command registers are to disable the Target capability and when generating the core in Host-Bridge mode it will hardwired the Master enable (mstr_ena) bit to 1.