For Stratix®, Cyclone® and earlier families, there is no read clock (rdclk) sensitivity on aclr. For Stratix II, Cyclone II, and newer device families, the rdclk sensitivity on aclr is removed beginning with the Quartus® II software version 5.1. The dcfifo megafunction automatically inserts an internal rdclk / aclr synchronization register for these devices, beginning with version 5.1.
However, the megafunction does not automatically insert an internal write clock (wrclk) synchronization register for aclr, because doing so may affect latency depending on aclr timing. The Single & Dual-Clock FIFO Megafunctions User Guide (PDF) explains how you can manually add a synchronization register between aclr and wrclk.