Article ID: 000079580 Content Type: Troubleshooting Last Reviewed: 01/01/2015

Are there any additional layout guidleines for UniPHY based DDR3 controller other than the information given in the External Memory Interface Handbook?

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Description

Yes, there are additional guidelines that are not in the current External Memory Interface Handbook. These design guidelines will be added in the next version of the handbook. 

Following these rules will help improve resync/write leveling timing for UniPHY based DDR3 interface; these rules don\'t affect ALTMEMPHY based interface.

Link to the document with the additional guidelines is given below:

DDR3 UniPHY Layout Guidelines (DOC)

Related Products

This article applies to 1 products

Stratix® IV GX FPGA