Article ID: 000079424 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the power source for Cyclone® II dedicated clock input pins when configured for the LVDS or LVPECL I/O standard?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description When Cyclone II dedicated clock input pins are configured for the LVDS or LVPECL I/O standard for input operations, the differential buffer is powered by VCCINT, not VCCIO.  Thus, the VCCIO does not have to be 2.5V when you use LVDS or LVPECL I/O standards on the dedicated clock input pins for input operations. 

Related Products

This article applies to 1 products

Cyclone® II FPGA