Article ID: 000078658 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Why does the output of altddio_out still toggle when the outclocken port is deasserted?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The outclocken port for the ddio_out only controls the high and low registers and not the output mux. The mux is controlled by a non-gated clock. Hence the output is unaffected when outclocken is deasserted.

If you wish to disable the output, use the output enable port.

Related Products

This article applies to 1 products

Cyclone® III FPGAs