Article ID: 000078266 Content Type: Troubleshooting Last Reviewed: 04/22/2013

Why do I see "VIOLATION ON DATAC" Vital timing violations in my Stratix device gate-level simulation for paths which are inactive?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software,  gate-level simulation models for Stratix® and Stratix GX devices incorrectly allow transitioning signals to propagate through the ASDATA port of internal cells to the destination register even when the ASDATA signal is gated by an inactive SLOAD signal. This may result in timing violations in your gate-level simulation.

    Resolution

    To work around this problem, insert logic to synchronize the signal and avoid the timing violation.

    This problem is fixed beginning with the Quartus II software version 12.0.

    Related Products

    This article applies to 2 products

    Stratix® FPGAs
    Stratix® GX FPGA