Article ID: 000078192 Content Type: Troubleshooting Last Reviewed: 04/12/2023

Why do I get minimum period timing violation in UniPHY-based DDR3 SDRAM Controller on a Stratix® V device?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see minimum period violations on address or command data-path in the Quartus® II software version 11.1SP2 and earlier if the UniPHY-based DDR3 SDRAM memory interface design in a Stratix® V device is combined with user logic that has packed registers in the periphery.

    Resolution

    This problem is fixed starting with the Quartus® II software version 12.0.

    Related Products

    This article applies to 4 products

    Stratix® V GT FPGA
    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GX FPGA

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